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ITF86130SK8T
TM
Data Sheet
June 2000
File Number
4798.4
14A, 30V, 0.0078 Ohm, N-Channel, Logic Level, Power MOSFET Packaging
SO8 (JEDEC MS-012AA)
BRANDING DASH
Features
* Ultra Low On-Resistance - rDS(ON) = 0.0078, VGS = 10V - rDS(ON) = 0.010, VGS = 4.5V - rDS(ON) = 0.012, VGS = 4.0V * Gate to Source Protection Diode * Simulation Models - Temperature Compensated PSPICETM and SABER Electrical Models - Spice and SABER Thermal Impedance Models - www.intersil.com * Peak Current vs Pulse Width Curve
5 1 2 3 4
Symbol
SOURCE(1) SOURCE(2) DRAIN(8) DRAIN(7)
* Transient Thermal Impedance Curve vs Board Mounting Area * Switching Time vs RGS Curves
Ordering Information
PART NUMBER PACKAGE SO8 86130 BRAND ITF86130SK8T
SOURCE(3) GATE(4)
DRAIN(6) DRAIN(5)
NOTE: When ordering, use the entire part number. ITF86130SK8T is available only in tape and reel.
Absolute Maximum Ratings
TA = 25oC, Unless Otherwise Specified ITF86130SK8T 30 30 20 14.0 12.0 7.0 7.0 Figure 4 2.5 20 -55 to 150 300 260 UNITS V V V A A A A A W mW/oC oC
oC oC
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Drain Current Continuous (TA= 25oC, VGS = 10V) (Figure 2) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TA= 25oC, VGS = 4.5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TA= 100oC, VGS = 4.5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Continuous (TA= 100oC, VGS = 4.0V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL Package Body for 10s, See Tech brief TB370 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg NOTES: 1. TJ = 25oC to 125oC. 2. 50oC/W measured using FR-4 board with 0.76in2 (490.3mm2) copper pad at 10s.
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. PSPICE(R) is a registered trademark of MicroSim Corporation. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright (c) Intersil Corporation 2000
ITF86130SK8T
Electrical Specifications
PARAMETER OFF STATE SPECIFICATIONS Drain to Source Breakdown Voltage Zero Gate Voltage Drain Current Gate to Source Leakage Current ON STATE SPECIFICATIONS Gate to Source Threshold Voltage Drain to Source On Resistance VGS(TH) rDS(ON) VGS = VDS, ID = 250A (Figure 10) ID = 14.0A, VGS = 10V (Figures 8, 9) ID = 7.0A, VGS = 4.5V (Figure 8) ID = 7.0A, VGS = 4.0V (Figure 8) THERMAL SPECIFICATIONS Thermal Resistance Junction to Ambient RJA Pad Area = 0.76 in2 (490.3 mm2) (Note 2) Pad Area = 0.054 in2 (34.8 mm2) (Figure 20) Pad Area = 0.0115 in2 (7.42 mm2) (Figure 20) SWITCHING SPECIFICATIONS (VGS = 4.5V) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time SWITCHING SPECIFICATIONS (VGS = 10V) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time GATE CHARGE SPECIFICATIONS Total Gate Charge Gate Charge at 5V Threshold Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge CAPACITANCE SPECIFICATIONS Input Capacitance Output Capacitance Reverse Transfer Capacitance CISS COSS CRSS VDS = 25V, VGS = 0V, f = 1MHz (Figure 12) 3050 675 285 pF pF pF Qg(TOT) Qg(5) Qg(TH) Qgs Qgd VGS = 0V to 10V VGS = 0V to 5V VGS = 0V to 1V VDD = 15V, ID = 12.0A, Ig(REF) = 1.0mA, (Figures 13, 16, 17) 58 31.5 3 9.5 12 nC nC nC nC nC td(ON) tr td(OFF) tf VDD = 15V, ID = 14.0A, VGS = 10V, RGS = 5.1 (Figures 15, 18, 19) 14 106 49 69 ns ns ns ns td(ON) tr td(OFF) tf VDD = 15V, ID = 7.0A,VGS = 4.5V, RGS = 4.7 (Figures 14, 18, 19) 23 84 33 42 ns ns ns ns 50 152 189
oC/W oC/W oC/W
TA = 25oC, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
BVDSS IDSS IGSS
ID = 250A, VGS = 0V (Figure 11) VDS = 30V, VGS = 0V VGS = 20V
30 -
-
10 10
V A uA
1.5 -
0.0058 0.007 0.008
2.5 0.0078 0.010 0.012
V
Source to Drain Diode Specifications
PARAMETER Source to Drain Diode Voltage Reverse Recovery Time Reverse Recovered Charge SYMBOL VSD trr QRR ISD = 12.0A ISD = 12.0A, dISD/dt = 100A/s ISD = 12.0A, dISD/dt = 100A/s TEST CONDITIONS MIN TYP 0.79 33 32 MAX UNITS V ns nC
2
ITF86130SK8T Typical Performance Curves
1.2 POWER DISSIPATION MULTIPLIER 1.0 0.8 0.6 0.4 0.2 0 0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC) 15 VGS = 10V, RJA = 50oC/W
ID, DRAIN CURRENT (A)
12
9
6
3
VGS = 4.0V, RJA = 189oC/W
0 25 50 75 100 125 150 TA , AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs AMBIENT TEMPERATURE
3 1 THERMAL IMPEDANCE ZJA, NORMALIZED DUTY CYCLE - DESCENDING ORDER 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 10-2 10-1 100 101 102 103 RJA = 50oC/W
0.1
0.01
SINGLE PULSE 0.001 10-5 10-4 10-3
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
2000 1000 IDM, PEAK CURRENT (A)
RJA = 50oC/W
TA = 25oC FOR TEMPERATURES ABOVE 25oC DERATE PEAK CURRENT AS FOLLOWS: I = I25 150 - TA 125
100
VGS = 4.5V
TRANSCONDUCTANCE MAY LIMIT CURRENT IN THIS REGION 10 10-5 10-4 10-3 10-2 10-1 t, PULSE WIDTH (s) 100 101 102 103
FIGURE 4. PEAK CURRENT CAPABILITY
3
ITF86130SK8T Typical Performance Curves
500 RJA = 50oC/W SINGLE PULSE TJ = MAX RATED TA = 25oC 100s
(Continued)
60 50 40
ID , DRAIN CURRENT (A)
100
ID , DRAIN CURRENT (A)
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDD = 15V
TJ = 25oC
TJ = 150oC 30 TJ = -55oC 20 10 0
10 OPERATION IN THIS AREA MAY BE LIMITED BY rDS(ON) 1 1 10
1ms
10ms 100
2.0
2.5
3.0
3.5
4.0
VDS , DRAIN TO SOURCE VOLTAGE (V)
VGS , GATE TO SOURCE VOLTAGE (V)
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
FIGURE 6. TRANSFER CHARACTERISTICS
60 50 ID, DRAIN CURRENT (A) 40 30 20 10 0 0
VGS = 10V VGS = 5V VGS = 4.5V
VGS = 4V rDS(ON), DRAIN TO SOURCE ON RESISTANCE (m)
20
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX ID = 14A
VGS = 3.5V
16
12
PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX
8
ID = 5A
VGS = 3V TA = 25oC
4 0.2 0.4 0.6 0.8 1.0 2 4 6 8 10 VDS , DRAIN TO SOURCE VOLTAGE (V) VGS , GATE TO SOURCE VOLTAGE (V)
FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT
1.6 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 14A NORMALIZED GATE THRESHOLD VOLTAGE
1.2 VGS = VDS, ID = 250A
1.0
1.3
0.8
1.0
0.6
0.7 -80
0.4 -40 0 40 80 120 160 -80 -40 0 40 80 120 160 TJ, JUNCTION TEMPERATURE (oC) TJ, JUNCTION TEMPERATURE (oC)
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE
4
ITF86130SK8T Typical Performance Curves
1.2 NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A CISS = CGS + CGD
(Continued)
5000
C, CAPACITANCE (pF)
1.1
COSS CDS + CGD
1000
1.0
CRSS = CGD 0.9 -80 VGS = 0V, f = 1MHz -40 0 40 80 120 160 200 0.1 1.0 10 30 VDS , DRAIN TO SOURCE VOLTAGE (V)
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
10 VGS , GATE TO SOURCE VOLTAGE (V) VDD = 15V SWITCHING TIME (ns) 8
400 VGS = 4.5V, VDD = 15V, ID = 7.0A 300 tr 200
6
4 WAVEFORMS IN DESCENDING ORDER: ID = 12A ID = 2A 0 10 20 30 40 50 60
tf td(OFF)
2
100 td(ON) 0 0 10 20 30 40 50
0 Qg, GATE CHARGE (nC)
RGS, GATE TO SOURCE RESISTANCE ()
NOTE: Refer to Intersil Application Notes AN7254 and AN7260. FIGURE 13. GATE CHARGE WAVEFORMS FOR CONSTANT GATE CURRENT
FIGURE 14. SWITCHING TIME vs GATE RESISTANCE
400 VGS = 10V, VDD = 15V, ID = 14A td(OFF)
SWITCHING TIME (ns)
300 tf 200 tr 100 td(ON) 0 0 10 20 30 40 50 RGS, GATE TO SOURCE RESISTANCE ()
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
5
ITF86130SK8T Test Circuits and Waveforms
VDS RL VDD VDS VGS = 10V VGS
+
Qg(TOT)
Qg(5) VDD VGS VGS = 1V 0 Qg(TH) Qgs Ig(REF) 0 Qgd VGS = 5V
DUT Ig(REF)
FIGURE 16. GATE CHARGE TEST CIRCUIT
FIGURE 17. GATE CHARGE WAVEFORMS
tON RL VDS VGS VGS
+
tOFF td(OFF) tr tf 90%
td(ON) VDS
90%
0V RGS DUT 90% VGS 0 10% 50% PULSE WIDTH 50% 0 10% 10%
FIGURE 18. SWITCHING TIME TEST CIRCUIT
FIGURE 19. SWITCHING TIME WAVEFORM
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the thermal resistance of the heat dissipating path determines the maximum allowable device power dissipation, PDM , in an application. Therefore the application's ambient temperature, TA (oC), and thermal resistance RJA (oC/W) must be reviewed to ensure that TJM is never exceeded. Equation 1 mathematically represents the relationship and serves as the basis for establishing the rating of the part.
( T JM - T A ) P DM = -----------------------------Z JA
1. Mounting pad area onto which the device is attached and whether there is copper on one side or both sides of the board. 2. The number of copper layers and the thickness of the board. 3. The use of external heat sinks. 4. The use of thermal vias. 5. Air flow and board orientation. 6. For non steady state applications, the pulse width, the duty cycle and the transient thermal response of the part, the board and the environment they are in. Intersil provides thermal information to assist the designer's preliminary application evaluation. Figure 20 defines the RJA for the device as a function of the top copper (component side) area. This is for a horizontally positioned FR-4 board with 1oz copper after 1000 seconds of steady state power with no air flow. This graph provides the necessary information for calculation of the steady state junction temperature or power dissipation. Pulse applications can be evaluated using the Intersil device Spice
(EQ. 1)
In using surface mount devices such as the SO8 package, the environment in which it is applied will have a significant influence on the part's current and maximum power dissipation ratings. Precise determination of PDM is complex and influenced by many factors:
6
ITF86130SK8T
thermal model or manually utilizing the normalized maximum transient thermal impedance curve. Displayed on the curve are RJA values listed in the Electrical Specifications table. The points were chosen to depict the compromise between the copper board area, the thermal resistance and ultimately the power dissipation, PDM . Thermal resistances corresponding to other copper areas can be obtained from Figure 20 or by calculation using Equation 2. RJA is defined as the natural log of the area times a coefficient added to a constant. The area, in square inches is the top copper area including the gate and source pads.
R JA = 83.2 - 23.6 x
Copper pad area has no perceivable effect on transient thermal impedance for pulse widths less than 100ms. For pulse widths less than 100ms the transient thermal impedance is determined by the die and package. Therefore, CTHERM1 through CTHERM5 and RTHERM1 through RTHERM5 remain constant for each of the thermal models. A listing of the model component values is available in Table 1.
240 RJA = 83.2 - 23.6 * 200 RJA (oC/W) 189oC/W - 0.0115in2
ln (AREA)
ln ( Area )
160
152oC/W - 0.054in2
(EQ. 2)
The transient thermal impedance (ZJA) is also effected by varied top copper board area. Figure 21 shows the effect of copper pad area on single pulse transient thermal impedance. Each trace represents a copper pad area in square inches corresponding to the descending list in the graph. Spice and SABER thermal models are provided for each of the listed pad areas.
120
80 0.01
0.1 AREA, TOP COPPER AREA (in2)
1.0
FIGURE 20. THERMAL RESISTANCE vs MOUNTING PAD AREA
150 COPPER BOARD AREA - DESCENDING ORDER 0.04 in2 0.28 in2 0.52 in2 0.76 in2 1.00 in2
120 ZJA, THERMAL IMPEDANCE (oC/W)
90
60
30
0 10-1
100
101 t, RECTANGULAR PULSE DURATION (s)
102
103
FIGURE 21. THERMAL IMPEDANCE vs MOUNTING PAD AREA
7
ITF86130SK8T PSPICE Electrical Model
.SUBCKT ITF86130SK8T 2 1 3 ;
CA 12 8 2.00e-9 CB 15 14 2.15e-9 CIN 6 8 2.70e-9
LDRAIN
REV 23 Nov 1999
DBODY 7 5 DBODYMOD DBREAK 5 11 DBREAKMOD DESD1 91 9 DESD1MOD DESD2 91 7DESD2MOD DPLCAP 10 5 DPLCAPMOD EBREAK 11 7 17 18 37.19 EDS 14 8 5 8 1 EGS 13 8 6 8 1 ESG 6 10 6 8 1 EVTHRES 6 21 19 8 1 EVTEMP 20 6 18 22 1
LGATE
DPLCAP 10 RSLC2
5 DBREAK RLDRAIN
DRAIN 2 RSLC1 51 ESLC 50 EBREAK
5 51
ESG + GATE 1 RLGATE DESD1 91 DESD2 CIN EVTEMP 9 RGATE + 18 22 20 6 8 EVTHRES + 19 8 6
IT 8 17 1 LDRAIN 2 5 1.0e-9 LGATE 1 9 1.04e-9 LSOURCE 3 7 1.29e-10 MMED 16 6 8 8 MMEDMOD MSTRO 16 6 8 8 MSTROMOD MWEAK 16 21 8 8 MWEAKMOD
MSTRO LSOURCE 8 RSOURCE RLSOURCE 7 SOURCE 3
RBREAK 17 18 RBREAKMOD 1 RDRAIN 50 16 RDRAINMOD 3.50e-4 RGATE 9 20 1.13 RLDRAIN 2 5 10 RLGATE 1 9 9 10.4 RLSOURCE 3 7 1.29 RSLC1 5 51 RSLCMOD 1e-6 RSLC2 5 50 1e3 RSOURCE 8 7 RSOURCEMOD 4.55e-3 RVTHRES 22 8 RVTHRESMOD 1 RVTEMP 18 19 RVTEMPMOD 1 S1A S1B S2A S2B 6 12 13 8 S1AMOD 13 12 13 8 S1BMOD 6 15 14 13 S2AMOD 13 15 14 13 S2BMOD
S1A 12 S1B CA 13 + EGS 6 8 13 8
S2A 14 13 S2B CB + EDS 5 8 14 IT 15 17
-
-
VBAT 22 19 DC 1 ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*650),2))} .MODEL DBODYMOD D (IS = 4.33e-12 RS = 3.91e-3 TRS1 = 1.01e-3 TRS2 = 1.11e-6 CJO = 2.02e-9 TT = 3.02e-8 M = 0.50) .MODEL DBREAKMOD D (RS = 1.08e-1 TRS1 = 1.01e-3 TRS2 = 1.04e-7) .MODEL DESD1MOD D (BV = 16.4 Tbv1= -2.50e-3 N= 21 RS = 100) .MODEL DESD2MOD D (BV = 16.1 Tbv1= -2.50e-3 N= 21 RS = 100) .MODEL DPLCAPMOD D (CJO = 1.35e-9 IS = 1e-30 M = 0.50) .MODEL MMEDMOD NMOS (VTO = 2.28 KP = 10.00 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 1.13) .MODEL MSTROMOD NMOS (VTO = 2.65 KP = 275 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u) .MODEL MWEAKMOD NMOS (VTO = 1.92 KP = 0.10 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 11.3 RS = 0.1) .MODEL RBREAKMOD RES (TC1 = 9.98e-4 TC2 = 1.01e-7) .MODEL RDRAINMOD RES (TC1 = 3.78e-2 TC2 = 4.99e-5) .MODEL RSLCMOD RES (TC1 = 4.07e-3 TC2 = 2.25e-5) .MODEL RSOURCEMOD RES (TC1 = 1.00e-3 TC2 = 0) .MODEL RVTHRESMOD RES (TC1 = -2.79e-3 TC2 = -9.65e-6) .MODEL RVTEMPMOD RES (TC1 = -1.90e-3 TC2 = 0) .MODEL S1AMOD VSWITCH (RON = 1e-5 .MODEL S1BMOD VSWITCH (RON = 1e-5 .MODEL S2AMOD VSWITCH (RON = 1e-5 .MODEL S2BMOD VSWITCH (RON = 1e-5 .ENDS ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 ROFF = 0.1 VON = -4.0 VOFF= -0.6) VON = -0.6 VOFF= -4.0) VON = -0.5 VOFF= 0) VON = 0 VOFF= -0.5)
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
8
+
11 + 17 18
-
RDRAIN 16 21
DBODY
MWEAK
MMED
RBREAK 18 RVTEMP 19
VBAT +
8 22 RVTHRES
ITF86130SK8T SABER Electrical Model
REV 23 Nov 1999 template ITF86130SK8T n2,n1,n3 electrical n2,n1,n3 { var i iscl dp..model dbodymod = (is = 4.33e-12,rs=3.91e-3,trs1=1.01e-3,trs2=1.11e-6, cjo = 2.02e-9, tt = 3.02e-8, m = 0.50) dp..model dbreakmod = (rs=1.08e-1,trs1=1.01e-3,trs2=1.04e-7) dp..model desd1mod = (bv=16.4,tbv1=-2.50e-3,n1=21, rs=100) dp..model desd2mod = (bv=16.1,tbv1=-2.50e-3,n1=21, rs=100) dp..model dplcapmod = (cjo = 1.35e-9, is = 1e-30, m = 0.50) m..model mmedmod = (type=_n, vto = 2.28, kp = 10, is = 1e-30, tox = 1) m..model mstrongmod = (type=_n, vto = 2.65, kp = 275, is = 1e-30, tox = 1) DPLCAP 5 m..model mweakmod = (type=_n, vto = 1.92, kp = 0.10, is = 1e-30, tox = 1) sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.0, voff = -0.6) 10 sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -0.6, voff = -4.0) RSLC1 sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0) 51 sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0, voff = -0.5) RSLC2 c.ca n12 n8 = 2.00e-9 c.cb n15 n14 = 2.15e-9 c.cin n6 n8 = 2.70e-9 dp.dbody n7 n5 = model=dbodymod dp.dbreak n5 n11 = model=dbreakmod dp.desd1 n91 n9 = model=desd1mod dp.desd2 n91 n7 = model=desd2mod GATE dp.dplcap n10 n5 = model=dplcapmod 1 i.it n8 n17 = 1 l.ldrain n2 n5 = 1.00e-9 l.lgate n1 n9 = 1.04e-9 l.lsource n3 n7 = 1.29e-10
ESG + EVTEMP RGATE + 18 22 9 20 RLGATE DESD1 91 DESD2 LGATE 6 MSTRO CIN 8 RSOURCE RLSOURCE S1A 12 13 8 S1B 13 + EGS 6 8 EDS S2A 14 13 S2B CB + 5 8 14 IT 15 17 RBREAK 18 RVTEMP 19 ISCL DBREAK 11 DBODY MWEAK MMED EBREAK + 17 18
LDRAIN DRAIN 2 RLDRAIN
6 8 EVTHRES + 19 8
50 RDRAIN 21 16
-
LSOURCE 7
SOURCE 3
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u res.rbreak n17 n18 = 1, tc1 = 9.98e-4, tc2 = 1.01e-7 res.rdrain n50 n16 = 3.50e-4, tc1 = 3.78e-2, tc2 = 4.99e-5 CA res.rgate n9 n20 = 1.13 res.rldrain n2 n5 = 10 res.rlgate n1 n9 = 10.4 res.rlsource n3 n7 = 1.29 res.rslc1 n5 n51 = 1e-6, tc1 = 4.07e-3, tc2 = 2.25e-5 res.rslc2 n5 n50 = 1e3 res.rsource n8 n7 = 4.55e-3, tc1 = 1.00e-3, tc2 = 0 res.rvtemp n18 n19 = 1, tc1 = -1.90e-3, tc2 = 0 res.rvthres n22 n8 = 1, tc1 = -2.79e-3, tc2 = -9.65e-6 spe.ebreak n11 n7 n17 n18 = 37.19 spe.eds n14 n8 n5 n8 = 1 spe.egs n13 n8 n6 n8 = 1 spe.esg n6 n10 n6 n8 = 1 spe.evtemp n20 n6 n18 n22 = 1 spe.evthres n6 n21 n19 n8 = 1 sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod v.vbat n22 n19 = dc=1
VBAT +
-
-
8 RVTHRES
22
equations { i (n51->n50) +=iscl iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/650))** 2)) } }
9
ITF86130SK8T SPICE Thermal Model
REV 11 Nov 1999 ITF86130SK8T Copper Area = 0.04 in2 CTHERM1 th 8 2.0e-3 CTHERM2 8 7 5.0e-3 CTHERM3 7 6 1.0e-2 CTHERM4 6 5 4.0e-2 CTHERM5 5 4 9.0e-2 CTHERM6 4 3 1.2e-1 CTHERM7 3 2 0.5 CTHERM8 2 tl 1.3 RTHERM1 th 8 0.1 RTHERM2 8 7 0.5 RTHERM3 7 6 1.0 RTHERM4 6 5 5.0 RTHERM5 5 4 8.0 RTHERM6 4 3 26 RTHERM7 3 2 39 RTHERM8 2 tl 55
th JUNCTION
RTHERM1 8
CTHERM1
RTHERM2 7
CTHERM2
RTHERM3 6
CTHERM3
SABER Thermal Model
Copper Area = 0.04 in2 template thermal_model th tl thermal_c th, tl { ctherm.ctherm1 th 8 = 2.0e-3 ctherm.ctherm2 8 7 = 5.0e-3 ctherm.ctherm3 7 6 = 1.0e-2 ctherm.ctherm4 6 5 = 4.0e-2 ctherm.ctherm5 5 4 = 9.0e-2 ctherm.ctherm6 4 3 = 1.2e-1 ctherm.ctherm7 3 2 = 0.5 ctherm.ctherm8 2 tl = 1.3 rtherm.rtherm1 th 8 = 0.1 rtherm.rtherm2 8 7 = 0.5 rtherm.rtherm3 7 6 = 1.0 rtherm.rtherm4 6 5 = 5.0 rtherm.rtherm5 5 4 = 8.0 rtherm.rtherm6 4 3 = 26 rtherm.rtherm7 3 2 = 39 rtherm.rtherm8 2 tl = 55 } TABLE 1. Thermal Models COMPONENT CTHERM6 CTHERM7 CTHERM8 RTHERM6 RTHERM7 RTHERM8 0.04 in2 1.2e-1 0.5 1.3 26 39 55 0.28 in2 1.5e-1 1.0 2.8 20 24 38.7
RTHERM4 5
CTHERM4
RTHERM5 4
CTHERM5
RTHERM6 3
CTHERM6
RTHERM7 2
CTHERM7
RTHERM8
CTHERM8
tl
CASE
0.52 in2 2.0e-1 1.0 3.0 15 21 31.3
0.76 in2 2.0e-1 1.0 3.0 13 19 29.7
1.0 in2 2.0e-1 1.0 3.0 12 18 25
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ITF86130SK8T MS-012AA
8 LEAD JEDEC MS-012AA SMALL OUTLINE PLASTIC PACKAGE
E E1 1 e 2 A A1
INCHES SYMBOL A A1 b c MIN 0.0532 0.004 0.013 0.0075 0.189 0.2284 0.1497 MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.244 0.1574
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 5.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 6.20 4.00 NOTES 2 3 4
D 6
D
b
E E1 e H
5
h x 45o
0.050 BSC 0.0099 0.016 0.0196 0.050
1.27 BSC 0.25 0.40 0.50 1.27
c
L
L 0.060 1.52 0o-8o
0.004 IN 0.10 mm
0.050 1.27 0.024 0.6
0.155 4.0 0.275 7.0 MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE-MOUNTED APPLICATIONS
NOTES: 1. All dimensions are within allowable dimensions of Rev. C of JEDEC MS-012AA outline dated 5-90. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed 0.006 inches (0.15mm) per side. 3. Dimension "E1" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 0.010 inches (0.25mm) per side. 4. "L" is the length of terminal for soldering. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. Controlling dimension: Millimeter. 7. Revision 8 dated 5-99.
1.5mm DIA. HOLE
4.0mm USER DIRECTION OF FEED 2.0mm 1.75mm C L
MS-012AA
12mm TAPE AND REEL
12mm
8.0mm
40mm MIN. ACCESS HOLE 18.4mm COVER TAPE 13mm 330mm 50mm
GENERAL INFORMATION 1. 2500 PIECES PER REEL. 2. ORDER IN MULTIPLES OF FULL REELS ONLY. 3. MEETS EIA-481 REVISION "A" SPECIFICATIONS.
12.4mm
11

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